Q. Explain about set up time and hold time.
Set up time is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is accepted properly on the clock edge.
Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make sure it is sensed properly at the clock edge.
Q. What is skew, what are problems associated with it and how to minimize it?
In circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times.
This is typically due to two causes.
- Material flaw: This causes a signal to travel faster or slower than expected.
- Distance: if the signal has to travel the entire length of a circuit, it will likely (depending on the circuit’s size) arrive at different parts of the circuit at different times.
Clock skew can cause harm in two ways.
- Hold violation
- Set-up violation
Suppose that a logic path travels through combinational logic from a source flip-flop to a destination flip-flop. If the destination flip-flop receives the clock tick later than the source flip-flop, and if the logic path delay is short enough, then the data signal might arrive at the destination flip-flop before the clock tick, destroying there the previous data that should have been clocked through. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through.
If the destination flip-flop receives the clock tick earlier than the source flip-flop, then the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived.
A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.
Clock skew can be minimized by
- proper routing of clock signal (clock distribution tree)
- Putting variable delay buffer so that all clock inputs arrive at the same time.
Q. What is slack?
‘Slack’ is the amount of time that is measured from when an event ‘actually happens’ and when it ‘must happen’. The term ‘actually happens’ can also be taken as being a predicted time for when the event will ‘actually happen’.
When something ‘must happen’ can also be called a ‘deadline’. So another definition of slack would be the time from when something ‘actually happens’ (call this Tact) until the deadline (call this Tdead).
Slack = Tdead – Tact.
Q. What is difference between latch and flip-flop?
The main difference between latch and FF is that latches are level sensitive while FF is edge sensitive. They both require the use of clock signal and are used in sequential logic. For a latch, the output tracks the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes. FF on the other hand, will store the input only when there is a rising/falling edge of the clock.
Q. Difference between heap and stack?
The Stack is more or less responsible for keeping track of what’s executing in our code (or what’s been “called”). The Heap is more or less responsible for keeping track of our objects (our data, well… most of it – we’ll get to that later.).
Consider Stack as a series of boxes stacked one on top of the next. We keep track of what’s going on in our application by stacking another box on top every time we call a method (called a Frame). We can only use what’s in the top box on the stack. When we’re done with the top box (the method is done executing) we throw it away and proceed to use the stuff in the previous box on the top of the stack.
The Heap is similar except that its purpose is to hold information (not keep track of execution most of the time) so anything in our Heap can be accessed at any time. With the Heap, there are no constraints as to what can be accessed like in the stack.
Q. Difference between mealy and Moore state machine?
Mealy and Moore models are the basic models of state machines.
- A state machine which uses only Entry Actions, so that its output depends on the state, is called a Moore model.
- A state machine which uses only Input Actions, so that the output depends on the state and also on inputs, is called a Mealy model.
Choice of a model depends on the application, execution means (for instance, hardware systems are usually best realized as Moore models) and personal preferences of a designer or programmer.
Advantages and Disadvantages:
In Mealy as the output variable is a function both input and state, changes of state of the state variables will be delayed with respect to changes of signal level in the input variables, there are possibilities of glitches appearing in the output variables. Moore overcomes glitches as output dependent on only states and not the input signal level.
All of the concepts can be applied to Moore-model state machines because any Moore state machine can be implemented as a Mealy state machine, although the converse is not true.
Moore machine: the outputs are properties of states themselves… which means that you get the output after the machine reaches a particular state, or to get some output your machine has to be taken to a state which provides you the output. The outputs are held until you go to some other state Mealy machine:
Mealy machines give you outputs instantly, that is immediately upon receiving input, but the output is not held after that clock cycle.
Q. Difference between one hot and binary encoding?
Common classifications used to describe the state encoding of an FSM are Binary (or highly encoded) and One hot.
A binary-encoded FSM design only requires as many flip-flops as are needed to uniquely encode the number of states in the state machine. The actual number of flip-flops required is equal to the ceiling of the log-base-2 of the number of states in the FSM.
An onehot FSM design requires a flip-flop for each state in the design and only one flip-flop (the flip-flop representing the current or “hot” state) is set at a time in a one hot FSM design. For a state machine with 9- 16 states, a binary FSM only requires 4 flip-flops while a onehot FSM requires a flip-flop for each state in the design.
FPGA vendors frequently recommend using an onehot state encoding style because flip-flops are plentiful in an FPGA and the combinational logic required to implement an onehot FSM design is typically smaller than most binary encoding styles. Since FPGA performance is typically related to the combinational logic size of the FPGA design, onehot FSMs typically run faster than a binary encoded FSM with larger combinational logic blocks.
Q. What is significance of RAS and CAS in SDRAM?
SDRAM receives its address command in two address words.
It uses a multiplex scheme to save input pins. The first address word is latched into the DRAM chip with the row address strobe (RAS).
Following the RAS command is the column address strobe (CAS) for latching the second address word.
Shortly after the RAS and CAS strobes, the stored data is valid for reading.
Q. Explain some of applications of buffer?
1. They are used to introduce small delays
2. They are used to eliminate cross talk caused due to inter electrode capacitance due to close routing.
3. They are used to support high fan-out, eg:bufg
Q. What will happen if contents of register are shifter left, right?
We know that, in left shift all bits will be shifted left and LSB will be appended with 0 and in right shift all bits will be shifted right and MSB will be appended with 0.
It is expected is in a left shift value gets Multiplied by 2 e.g.: consider 0000_1110=14 a left shift will make it 0001_110=28, it the same fashion right shift will Divide the value by 2.